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https://www.quora.com/What-is-the-difference-between-ModelSim-Altera-VCS-and-NC-Verilog
Mar 07, 2019 · ModelSim is a function simulator from Mentor graphics for ASIC /FPGA designs. It supports both Verilog/SystemVerilog and VHDL languages, but have limited support for advanced System Verilog language (and specifically OVM/UVM/ etc. It can be used for Altera (now Intel) FPGA design simulations. Otherwise there is nothing like ModelSim-Altera.
https://eda-playground.readthedocs.io/en/latest/modelsim-uvm.html
UVM can be used with ModelSim 10.1d as long as the following coding style adjustments are followed: When creating a uvm_sequence , put the following in the constructor: do_not_randomize = 1'b1; class my_sequence extends uvm_sequence #( my_transaction ); function new (); // MUST BE SET when using ModelSim do_not_randomize = 1 'b1 ; endfunction
https://verificationacademy.com/forums/ovm/active/modelsim
The Verification Community is eager to answer your UVM, SystemVerilog and Coverage related questions. We encourage you to take an active role in the Forums by answering and commenting to any questions that you are able to.
https://www.mentor.com/products/fv/success/IME_OVM_CSS_11-08_final
An excellent history with Mentor Graphics® and the promise of full SystemVerilog support inspired them to adopt Questa® and the Open Verification Methodology (OVM), with excellent results. Two particularly tricky problems were resolved that would have …
https://forums.xilinx.com/t5/Synthesis/VHDL-2008-support/td-p/362505/page/2
Yes, I believe Aldec's tools (ActiveHDL and Riviera) have probably the best VHDL-2008 support so far. However, other vendors are catching / have caught up. Mentor's ModelSim is pretty decent in language support, supporting almost all the features of VHDL-2008, including type generics, package generics, and subprogram generics - which I used in the project I mentioned in my first post.
https://blogs.mentor.com/verificationhorizons/blog/2011/03/08/using-the-uvm-10-release-with-questa/
Migration from OVM to UVM. An OVM design can be migrated to UVM using a script. Many OVM designs can work without any hand coded changes or other intervention. It is a good idea to first get your design running on the latest version of OVM 2.1.2, before starting the migration process.
https://www.edaboard.com/showthread.php?114780-Systemverilog-OVM-(Open-Verification-Methodology)
Jan 15, 2008 · I have played around with Xilinx Modelsim/XE 6.2c -- that was the only "free" Modelsim to support Systemverilog to a reasonable degree (for Design only, no SVA or advanced verification features) That's a good starting point, but remember it is only …
https://docs.oracle.com/cd/E50245_01/E50249/html/vmcon-ovm-support.html
2.9 What Support is Available for Oracle VM? ... Oracle VM Support is an add-on component of Oracle's enterprise support package that offers an end-to-end single vendor support solution from the application to the disk. A single support call covers the entire Oracle …
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