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https://stackoverflow.com/questions/17670948/how-to-enable-ssse3-intrinsics-but-disable-their-use-in-compiler-optimization
Oct 27, 2016 · I have a code that uses SSSE3 intrinsic commands (note the triple S) and a runtime check whether to use it, therefore I assumed that the application should execute on CPUs without SSSE3 support. However, when using -mssse3 with -O1 optimization the compiler also inserts SSSE3 instructions which I didn't explicitly call, hence the program crashes.
https://gcc.gnu.org/onlinedocs/gcc/x86-Options.html
3.19.59 x86 Options. These ‘-m’ options are defined for the x86 family of computers.-march=cpu-type Generate instructions for the machine type cpu-type.In contrast to -mtune=cpu-type, which merely tunes the generated code for the specified cpu-type, -march=cpu-type allows GCC to generate code that may not run at all on processors other than the one indicated.
https://software.intel.com/en-us/forums/intel-isa-extensions/topic/379604
Neither icc nor gcc normally want tmmintrin.h included directly, as immintrin.h provides for including tmmintrin.h when SSSE3 or hgiht option is set, as well as the intrinsics headers for earlier instruction sets.
https://gcc.gnu.org/onlinedocs/gcc-4.5.3/gcc/i386-and-x86_002d64-Options.html
Therefore, if you upgrade to a newer version of GCC, the code generated option will change to reflect the processors that were most common when that version of GCC was released. ... SSE3 and SSSE3 instruction set support. atom Intel Atom CPU with 64-bit extensions, MMX, SSE, SSE2, SSE3 and SSSE3 instruction set support. k6 AMD K6 CPU with MMX ...
https://software.intel.com/en-us/cpp-compiler-developer-guide-and-reference-intrinsics-for-intel-supplemental-streaming-simd-extensions-3-ssse3
Dec 16, 2019 · Parent topic: Intrinsics Overview: Supplemental Streaming SIMD Extensions 3 (SSSE3) Addition Intrinsics Intrinsics for Intel® Supplemental Streaming …
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