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https://www.intel.com/content/www/us/en/support/products/81508/graphics-drivers/legacy-graphics/graphics-drivers-for-mobile-intel-965-express-chipset-family.html
Support product highlights, featured content, downloads and more for Graphics Drivers for Mobile Intel® 965 Express Chipset Family
https://www.intel.com/content/www/us/en/support.html
Intel® Customer Support home page. We appreciate all feedback, but cannot reply or give product support. Please do not enter contact information.
http://ixbtlabs.com/articles2/mainboard/i965-chipset.html
Intel 965 Express Chipsets with Official Support for Core 2 Duo/Extreme: ... Here is a brief list of the key features of the 965-series chipsets: Support for all "old" Celeron and Pentium processors (including dual-core processors) with 533/800/1066 MHz FSB, as well as all Core 2 Duo/Extreme processors ... Memory support. There was added 400 ...
http://www.cpu-upgrade.com/mb-Intel_(chipsets)/GM965_Express.html
Important: Below is a support list for the GM965 Express chipset, and not a support list for your motherboard, built on that chipset.The chipset is only one of key elements that determine CPU compatibility. Other key factors are: socket type, package type, maximum Thermal Design Power, BIOS version, CPU core name and stepping.
https://www.intel.com/assets/pdf/whitepaper/313207.pdf
Intel® 965 Express Chipset Family Memory Configuration White Paper 5 1 Introduction This document details the Intel® 965 Express chipset family (G)MCH’s technology enhancements, supported memory configurations, and memory organizations. It is intended for a technical audience interested in learning about the performance
https://ark.intel.com/content/www/us/en/ark/products/29821/intel-82gm965-graphics-and-memory-controller.html
Note that ECC memory support requires both processor and chipset support. ... Intel® Fast Memory Access is an updated Graphics Memory Controller Hub (GMCH) backbone architecture that improves system performance by optimizing the use of available memory bandwidth and reducing the latency of the memory accesses.
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