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https://android.googlesource.com/kernel/mediatek/+/045e24819c0deb2fe15306b8d38060beadb56d2f/drivers/dma/intel_mid_dma.c
* intel_mid_dma_tx_submit - callback to submit DMA transaction * @tx: dma engine descriptor * * Submit the DMA trasaction for this descriptor, start if ch idle ... * Perform a DMA memcpy. Note we support slave periphral DMA transfers only * The periphral txn details should be filled in slave structure properly
https://software.intel.com/en-us/forums/software-tuning-performance-optimization-platform-monitoring/topic/538135
We are using Xeon E3-1275v3 and C226 PCH on our board. I am aware that this system does not support I/OAT or NetDMA. Is there any user programmable DMA controller? We want to perform DMA transfers from the main memory (source) to PCIe devices …
https://www.kernel.org/doc/html/latest/driver-api/pci/p2pdma.html
PCI Peer-to-Peer DMA Support¶ The PCI bus has pretty decent support for performing DMA transfers between two devices on the bus. This type of transaction is henceforth called Peer-to-Peer (or P2P). However, there are a number of issues that make P2P transactions tricky to do in a perfectly safe way.
https://groups.google.com/d/topic/linux.kernel/cMM2nSQ5Wqs
Jun 23, 2010 · From: Vinod Koul <[email protected]> This patch add DMA drivers for DMA controllers in Langwell chipset of Intel(R) Moorestown platform and DMA controllers in Penwell of
http://lkml.iu.edu/hypermail/linux/kernel/1102.0/00918.html
SPI master controller driver for the Intel MID platform Medfield This driver uses the Penwell SSP controller and configures it to be a SPI device (spibus 3).
https://www.kernel.org/doc/html/latest/driver-api/dmaengine/client.html
For cyclic DMA, a callback function may wish to terminate the DMA via dmaengine_terminate_async(). Therefore, it is important that DMA engine drivers drop any locks before calling the callback function which may cause a deadlock. Note that callbacks will always be invoked from the DMA engines tasklet, never from interrupt context.
https://github.com/raspberrypi/linux/commit/6ede6dcd87aa32787f077b6556dce6b0de7d91e6
Oct 13, 2015 · In this repository All GitHub ↵ Jump to ... serial: 8250_mid: add support for DMA engine handling from UART MMIO The platforms that have this UART, but that don't have separate PCI device for the DMA Engine, need to create the HSU DMA Engine device separately. ... /* Intel MID Specific registers */ # define INTEL_MID_UART_PS 0x30 @@ -33,6 +34 ...
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