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The light came on when I saw the Opal Kelly product line - it was perfect for us. It has memory, USB, powerful FPGA with lots of I/O, and not much else. This is a fundamental value of Opal Kelly modules - they have the minimum configuration to be incredibly flexible and useful, without the cost and complexity of unnecessary accessories.
https://opalkelly.com/support/frequently-asked-questions/
Opal Kelly tries to maintain a release of the simulation libraries using the latest free ModelSim XE. These packages are available in either the installed FrontPanel application directory, or are available for download through our online forum. We do not typically support older versions of ModelSim XE because upgrading is free.
https://opalkelly.com/support/microblaze/
Note: This page is no longer supported and is here only for archival purposes. FrontPanel MicroBlaze Integration Design Flexibility Opal Kelly FrontPanel modules are powerful and flexible. They can be integrated into virtually any design environment in the FPGA. Interoperability Communication between a PC, MicroBlaze soft core processors, and other logic in the FPGA can …
https://opalkelly.com/products/
The SYZYGY Brain-1 is an open-source hardware SYZYGY Compatible carrier designed, manufactured, and sold by Opal Kelly. $324.95: XEM7320-A75T (Carrier) The XEM7320 is a USB 3.0 system integration platform with USB 3.0 support via the FrontPanel SDK, a Xilinx Artix-7 FPGA, and three SYZYGY ports. $549.95: SZG-ADC-LTC2264
https://opalkelly.com/products/lifecycle/
Opal Kelly products not listed above (such as the breakout boards, evaluation modules, and headers) are not lifecycle managed. Design files for the breakout boards are available on our Downloads page. For more information on these products, please contact Opal Kelly Support. Major Component Lifecycle
https://forums.opalkelly.com/t/readfrompipeout-latency-support/1645
Sep 15, 2019 · Hi Support Team Does ReadFromPipeOut call support any Read latency ? Per the signal /waveform description, it expects the data to be read , the next cycle EP_READ is asserted. This will work if the FIFO produces data in the very next cycle, when read and the address is presented. In most cases, where the FIFO is large and the IPs introduce latencys > 0 , it becomes hard to pipeline …
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