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https://www.xilinx.com/support/answers/51360.html
9 rows · This Answer Record contains child answer records covering various SystemVerilog …
https://www.xilinx.com/support.html
Xilinx Technical Support provides assistance to all types of inquiries except the following: Information on product availability, pricing, order lead times, and product end-of-life. Software and Reference Designs older than the last two major releases. (e.g., if 2019.1 is the current release, versions 2019.x and 2018.x are supported, but 2017.x ...
https://forums.xilinx.com/t5/Synthesis/Does-Vivado-support-SystemVerilog-Verilog-Unions/td-p/824977
Re: Does Vivado support SystemVerilog Verilog Unions? Jump to solution Note I have them actually RUNNING on the FPGA hardware, with 90% success and 10% workaround.
https://forums.xilinx.com/t5/Design-Entry/ISE-14-1-and-SystemVerilog/td-p/235270
We now have two major tools released in parallel with two versioning systems: 14.x for ISE and 2012.x for Vivado. System Verilog will not be supported in ISE 14.x. It's supported in Vivado for 7 series and future devices. You do need a speical license today for Vivado 2012.1, which your FAE will …
https://forums.xilinx.com/t5/Synthesis/SystemVerilog-support-ISE-12/td-p/62919
Hi! i was read a long time ago: Xilinx ISE will support SystemVerilog in v10. ok, now we have 11.3 (must update to 11.4) but SystemVerilog still "out of range". Can i expect ISE 12 to support SV for synthesis or i must look around for other (too expensive) tools like Synplify Pro? I'm sorry if my qu...
https://forums.xilinx.com/t5/Welcome-Join/IP-Integrator-systemverilog-interface-support/td-p/685249
Hi, I'd like to extract several AXI4 ports out from the IP Integrator and it is a lot of signals. So I think to add a user IP to the IP Integrator which will wrap the the AXI4 bus into a signal systemverilog interface. Does the IP Integrator support systemverilog interface? Thanks, Lior Glass
https://www.xilinx.com/support/documentation-navigation/design-hubs/dh0018-vivado-synthesis-hub.html
Solution Center and Known Issues Date AR55265 - Xilinx Solution Center for Vivado Synthesis 02/15/2016 AR70644 - 2018.x Vivado Synthesis - Known Issues Design Assistants for Vivado Synthesis Date AR51360 - Help with SystemVerilog Support 04/03/2013 AR55160 - Help with Synthesis HDL Attribute Support 06/04/2014
https://www.xilinx.com/support/download.html
Please note that Vivado 2017.3 is the last release that will support Solaris operating system. Xilinx will continue to support Window and Linux operating systems. Floating Server Tools Windows (Flex v11.14.1.0) (ZIP - 21.25 MB)
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