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https://www.mentor.com/products/fv/multimedia/modelsim-to-questa-core--adopting-assertion-based-verification-to-improve-your-fpga-debug-and-design-quality
The assertions also turbo-charge time-to-debug productivity because they identify functional bugs much closer to the root cause; significantly shortening the causality traceback by hours or even days. Questa® Core enables ABV through support of SystemVerilog Assertion (SVA) constructs and the Property Specification Language (PSL).
https://forums.intel.com/s/question/0D50P00003yyKA6SAM/which-version-of-modelsim-support-system-verilog-assertions?language=en_US
ModelSim-Altera Starter Edition software is the same as ModelSim-Altera Edition software except for two areas. ModelSim-Altera Starter Edition’s simulation performance is lower than ModelSim-Altera Edition and has a line limit of 10,000 executable lines compared to the unlimited number of lines allowed in the ModelSim-Altera Edition.
https://www.xilinx.com/support/documentation-navigation/design-hubs/dh0010-vivado-simulation-hub.html
UG900 - Does the Vivado Simulator Support SystemVerilog? 10/30/2019 UG900 - Does the Vivado Simulator Support DPI? 10/30/2019 AR64139 - What Do I Do If My Simulation Fails? AR64059 - When Do I Use the UniMacro Library? AR64061 - When Do I Use the UNIFAST Library?
https://www.mentor.com/company/higher_ed/modelsim-student-edition
Oct 29, 2019 · ModelSim PE Student Edition is intended for use by students in pursuit of their academic coursework and basic educational projects. For more complex projects, universities and colleges have access to ModelSim and Questa, through the Higher Education Program. ModelSim PE Student Edition is not be used for business use or evaluation.
https://www.mentor.com/products/fv/modelsim/
Comprehensive support of Verilog, SystemVerilog for Design, VHDL, and SystemC provide a solid foundation for single and multi-language design verification environments. ModelSim’s easy to use and unified debug and simulation environment provide today’s FPGA designers both the advanced capabilities that they are growing to need and the ...
https://forums.intel.com/s/question/0D50P00003yyNBaSAM/how-to-simulate-in-systemverilog-with-alteramodelsim?language=en_US
The Modelsim-Altera-Edition will allow you to process SystemVerilog, but it will not allow you to mix languages (VHDL + Verilog), so you have to generate things like SOPC system components in Verilog. The full version of Modelsim and Mentor Graphics Questa supports mixed language design, SystemVerilog assertions, etc. Cheers, Dave
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